
module mycpu_float (
    input clk,
    input       [3:0] floatCmd,
    input       [3:0] floatCmd_result,
    input      [31:0] regfileA,
    input      [31:0] regfileB,
    output reg [31:0] floatResult
  );


wire [31:0] floatResult_add_sub;
wire [31:0] floatResult_mul;
wire [31:0] floatResult_div;
wire        floatResult_aeb ;
wire        floatResult_agb ;
wire        floatResult_ageb;
wire        floatResult_alb ;
wire        floatResult_aleb;
wire        floatResult_aneb;
wire [31:0] floatResult_convert;
float_add_sub	float_add_sub_inst (
	.add_sub ( floatCmd[0] ? 0 : 1 ),//altera +1 -0
	.clock ( clk ),
	.dataa ( regfileA ),
	.datab ( regfileB ),
	.result ( floatResult_add_sub )
);
float_mul	float_mul_inst (
	.clock ( clk ),
	.dataa ( regfileA ),
	.datab ( regfileB ),
	.result ( floatResult_mul )
);
float_div	float_div_inst (
	.clock ( clk ),
	.dataa ( regfileA ),
	.datab ( regfileB ),
	.result ( floatResult_div )
);
float_cmp	float_cmp_inst (
	.clock ( clk ),
	.dataa ( regfileA ),
	.datab ( regfileB ),
	.aeb  ( floatResult_aeb  ),
	.agb  ( floatResult_agb  ),
	.ageb ( floatResult_ageb ),
	.alb  ( floatResult_alb  ),
	.aleb ( floatResult_aleb ),
	.aneb ( floatResult_aneb )
);
float_convert float_convert_inst (
	.clock ( clk ),
	.dataa ( regfileA ),
	.result( floatResult_convert )
);

always @(*) begin


  case(floatCmd_result)
    0 : begin//-mcustom-fadds=0
      floatResult <= floatResult_add_sub;
    end
    1 : begin//-mcustom-fsubs=1
      floatResult <= floatResult_add_sub;
    end
    2 : begin//-mcustom-fmuls=2
      floatResult <= floatResult_mul;
    end
    3 : begin//-mcustom-fdivs=3
      floatResult <= floatResult_div;
    end
    8 : begin//-mcustom-fcmpeqs=8
      floatResult <= floatResult_aeb;
    end
    9 : begin//-mcustom-fcmpges=9
      floatResult <= floatResult_ageb;
    end
    10 : begin//-mcustom-fcmpgts=10
      floatResult <= floatResult_agb;
    end
    11 : begin//-mcustom-fcmples=11
      floatResult <= floatResult_aleb;
    end
    12 : begin//-mcustom-fcmplts=12
      floatResult <= floatResult_alb;
    end
    13 : begin//-mcustom-fcmpnes=13
      floatResult <= floatResult_aneb;
    end
    14 : begin//-mcustom-fixsi=14
      floatResult <= floatResult_convert;
    end
    // 15 : begin//fmin
    //   floatResult <= floatResult_agb ? regfileB : regfileA;
    // end
    default: begin
      floatResult <= 0;
    end
  endcase
end
// Conversions:

// ‘fextsd’
// Conversion from single precision to double precision.

// ‘ftruncds’
// Conversion from double precision to single precision.

// ‘fixsi’, ‘fixsu’, ‘fixdi’, ‘fixdu’
// Conversion from floating point to signed or unsigned integer types, with truncation towards zero.

// ‘floatis’, ‘floatus’, ‘floatid’, ‘floatud’
// Conversion from signed or unsigned integer types to floating-point types.

endmodule
